In an architecture, such as the manifold array (ManArray) processor, VLIWs are created from multiple short instruction words (SIWs), stored in a VLIW memory (VIM), and executed by an SIW execute VLIW (XV) instruction. The pipeline used in the processor is a dynamically reconfigured pipeline which supports a distributed VIM in each of the processing elements (PEs) in the array processor. See, for example, “Methods and Apparatus to Dynamically Reconfigure the Instruction Pipeline of An Indirect Very Long Instruction Word Scalable Processor” U.S. patent application Ser. No. 09/228,374 filed Jan. 12, 1999, and incorporated by reference herein in its entirety.
The execution phase of the pipeline is relatively simple consisting of either single or dual execution cycles depending upon the instruction. This pipeline works fine for relatively simple instruction types, but has certain limitations in its support of more complex instructions which cannot complete their execution within a two-cycle maximum limit specified by an initial ManArray implementation. A VLIW processor, having variable execution periods can cause undesirable complexities for both implementation and for programming. It thus became desirable to solve the problem of how to add more complex instruction types in a SIMD array indirect VLIW processor such as the ManArray processor to support the evolution of this processor to a further range of applications.